Grants and Funded Research Received by Peter M. Kogge:

• Sandia National Labs, “X-caliber,” 6/10 through 6/12. Part of the DARPA Ubiquitous High Performance Computing (UHPC) program to develop architectures for exascale computers.
• Center for Circuit & System Solutions (C2S2), 7/10 through 7/11. “Microarchitectural Design on Regular Fabric Patterning.”
• DARPA through Georgia Tech, "ExaScale Computing Software Study," 6/08 thru 12/09. Participate in working group developing challenges to software for Exascale computing systems.
• DARPA through Georgia Tech, "ExaScale Computing Feasibility Study," 5/07 thru 12/08 Lead a study group in understanding the course of mainstream computing technology, and determining whether or not it would allow a 1,000X increase in the computational capabilities of computing systems by the 2015 time frame.
• NSF CRI (co I with Jay Brockman as PI), "Development of a Research Infrastructure for the Multithreaded Computing Community Using the Cray Eldorado platform," 2007-2012
• DARPA through AFRL, (with Jay Brockman) "SASIC: Structured Asic," 7/1/07 thru 12/31/08. Develop layout and architectural approaches for lower cost and time to develop structured ASIC chips.
• DARPA through AFRL, (with Jay Brockman) "Feasibility of G4 FETs for Dynamically Reconfigurable Structures to Support Mixed Memory and Logic Computation Structures," 4/1/07 thru 6/30/08. Explore potential of 4 gate FET to simplify design of FPGA-like logic blocks.
• DARPA through AFRL Grant FA8750-06-1-0234, (with Jay Brockman) "Design and Simulation of a Programmable Memory/Multiplier Array Using G4-FET Technology," 7/11/06 through 1/7/07. Explore use of 4 gate FET transistors in structured ASIC cell designs for both logic and memory.
• Sandia National Labs, "At the Memory Floating Point Architecture Research," 11/01/04 through 10/31/07. Investigate what kinds and how much floating point computation in large scientific codes could be profitably moved to the neighborhood of a memory.
• DARPA through NTE Inc (Subsidiary of Cray Inc.), "LWP Studies in support of the Cascade Project," 7/8/03 through 7/7/06. Design of a PIM-based memory system for a trans-petaflop system as part of DARPA HPCS Phase 2 program.
• Sandia National Labs, "Understanding Performance of New PIM-Based Execution Models," 2/1/03 through 12/31/03.
• DARPA through Cray Inc., "High Productivity Computing Systems," 6/14/02 through 6/30/03. Architectures for trans-Petaflops computers.
• NSF, "NIRT: Architectures and Devices for Quantum Dot Cellular Automata," 7/15/02 through 7/14/07. Fabrication techniques, experiments, and architectures for complex QCA-based systems.
• NSF, "Molecular Architecture Workshop." 9/1/01 through 8/31/02. Host a workshop on the relationship of architectures to emerging nanotechnologies.
• Semiconductor Research Corp., "Memory Architectures in QCA," 9/1/00 through 8/31/04. Design and characterize memory structures developed from QCA devices.
• DARPA, "Morphable Computer Architectures for Highly Energy Aware Systems," 5/19/00 through 9/30/03. Develop computer architecture where energy/performance characteristics can be shaped to meet available energy profiles, and matching support tools.
• JPL, "Quantum dot Cellular Automata Defect Tolerant Architectures," 9/1/00 through 8/31/03. Definition of fault models in QCA and architectures that handle them.
• JPL, "Phase III HTMT PIM Memory System Design," 1/1/00 to 5/31/01. As part of HTMT petaflops project, to more completely design PIM node architectures to implement multi-level smart memory hierarchy and support alternative execution models.
• DARPA, "DIVA: Data IntensiVe Architecture," 4/98 to 3/01. Joint project with USC/ISI to architect and fabricate a PIM device using leading edge DRAM technology and to construct multi-chip memory systems capable of performing "in-memory" access, search, and processing of irregular data structures for data intensive applications.
• Lockheed Martin, Owego, "System Concepts for PIM Accelerators," 9/1/98 to 8/31/99. Prototype software and applications for EXASPHERE M32R/D based PIM prototype accelerator.
• JPL, "Hybrid Technology MultiThreaded (HTMT) System: PIM Based Memory Hierarchy," 5/23/97 to 12/31/99. Joint multi-university project to architect complete petaflops-level machine capable of deployment in 2007 timeframe.
• Lockheed Martin, Owego, "PIM Prototype System Demonstrator," 9/1/97 to 8/31/98. Construction of EXASPHERE: multi M32R/D based "smart memory" PCI card.
• Extension of JPL Grant No. 960587, "Scalable Spaceborne Computing Using PIM Technology." A PIM chip architecture for deep space applications.
• NSF CDA-9712921, "From Bits to Chips: A Multidisciplinary Curriculum for Microelectronics System Design Education," Sept. 1997 to July 31, 2000. Reworking parts of the undergraduate computer science, computer engineering, and electrical engineering curricula to provide a comprehensive computer design thread that spans from instruction set and compiler issues, through computer organization, to fabrication of complete CMOS microprocessors.
• NSF ACS96-12028, "Point Design for 100 TF PIM-based Computers," Sept. 1, 1996 to August 31, 1997. Architectural studies of potential machines designed with PIM technology to meet 100 TFs in 2004 timeframe.
• JPL Grant No. 960587, "Scalable Spaceborne Computing Using PIM Technology," May 15, 1996 to Nov. 15, 1996. Applicability of PIM technology to potentially satisfy deep space exploration platforms.
• Mayo Foundation/ARPA, "PIM Based Accelerator Technology Infrastructure," May 1, 1996 to May 31, 1997. Identify state of the art in PIM technology and roadblocks to its utilization in accelerators.
• NEC Research Institute, "High Speed Content-based Image Retrieval Techniques," April 1, 1996 to May 31, 1997. Sizing of potential PIM-based image search engines for very large image database problems.
• NASA Grant # NAG5-2998, "Processing-In-Memory Architectures Peta(Fl)ops Computing," July, 1995 to July 1996. Design space for PIM technology that is relevant to possible petaflops level computers.
• NSF Grant #MIP-9503682, "Architectural Techniques for Inherently Low Power Computers," Sept. 1995 to August, 1998. Techniques starting at the instruction set architecture level that allow design of inherently low power computer architectures.