Professional Activities by Peter M. Kogge:

Panels

• Member, Interim Interim Council for CRA Computing Community Consortium, Nov. 2006-2007
• Panel Member, National Research Council's Joint IED Defeat Organization (JIEDDO) Review Committee, Oct. 2006 - present
• Panel member, HPC subpanel to Panel on Disruptive Technologies for US DoD Defense Science Board, 2005-2006
• Board member and chair of Digital Panel, National Research Council's Army Research Lab's Technical Assessment Board (ARLTAB), 2005-present
• Chaired the U.S. Army's Research Laboratory's Technical Assessment Board's Digitization and Communication Sciences Panel's team to review nanotechnologies activities at ARL under the auspices of the National Research Council, summer, 2004.

Editorships:

• Associate Editor, ACM Journal on Emerging Technologies in Computing Systems, 2004-present
• Assoc. Editor, IEEE Transactions on Computers, 1986-1989

Conference/Workshop Chair

• Chair of Steering Committee for Workshop on Programming Languages for High Performance Computing, Sandia National Labs, Computer Science Research Institute (CSRI), Albuquerque, NM, Dec. 2006.
• Organizer and Moderator of Advanced Circuits Forum on Multicore Architectures, Designs, and Implementation Challenges, Int. Solid State Circuits Conf. (ISSCC), San Francisco, Feb. 10, 2006.
• Session Organizer and Chair: Custom Architectures, High End Computing Revitalization Task Force (HECRTF), Washington D.C., June 17-18, 2003.
• Program Co-Chair, 12th Great Lakes Symp. on VLSI, NYC, March 2002
• Kogge, Peter M., Workshop Organizer, Molecular Architecture Workshop, Nov. 12-13, 2001.
• Program Vice-Chair, 7th Symp. on the Frontiers of Massively Parallel Computation, Feb. 1999
• Program Chair, 6th Symp. on the Frontiers of Massively Parallel Computation, Oct. 1996
• Co-Chair, Petaflops Architecture Workshop, Mandely Beach, CA, April 1996
• General Technical Chairman, 1989 Int. Conf. on Parallel Processing, 1989

Conference/Workshop Program Committees:

• Workshop on Multithreaded Architectures and Applications (MTAAP), 2009, 2010
• Int. Symp. on Microarchitecture (MICRO), 2005
• Computing Frontiers Conference, Emerging Nanotechnologies Track, 2005.
• Digital Group, Int. Solid State Circuits Conference (ISSCC): 2003, 2004, 2005, 2006, 2007
• Int. Conf. on Parallel Processing, 2005
• The 2nd Workshop on Intelligent Memory Systems, ASPLOS 2000
• Int. Workshop on Innovative Architectures, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
• Architecture Program Committee, Supercomputing Conference, 1998, 1999, 2000, 2002, 2003, 2004, 2005
• Int. Symp. on Low Power Electronic Design (ISLPED), 2001, 2002, 2003
• Petaflops Software Workshop, Bodega Bay, CA, June 1996
• Int. Conf. Supercomputing, 1996, 2003, 2004, 2005, 2006
• Int. Symp. Computer Arch., 1986, 1994, 1999
• 1990 Workshop on VLSI and AI, Oxford Univ., 1990
• IEEE Symp. on Logic Programming, 1988, 1989
• Program Committee for Fault Tolerant Computing IBM ITL

Other

• Member Notre Dame Center for Research Computing Director Search committee, 2005-2006
• Member Notre Dame Engineering Dean Search committee, 2005-present
• Elected representative from Engineering to Notre Dame Graduate Council, 2002-2003
• Member, AIAA Committee on Real Time Artificial Intelligence, 1992 to 1994
• Member, Industrial Research Fellows Affiliates, 10/92
• Member, NSF Computer and Computation Research Advisory Board, 1991-1992
• Member, External Research Advisory Group, NY State Center for Software and Computer Applications, (CASE Center at Syracuse Univ.), 1988 to 1994
• IEEE Distinguished Visitor, 1988-1990
• Member, Faculty Search Committee, SUNY Binghamton, 9/83-9/84