Pre-lab Tasks:

1. Consider an RC circuit whose input is a PWM signal with a period $T$ and duty cycle $T_1/T$. Derive an equation for the signal's steady state value as a function of $R$, $C$, and the PWM signal's duty cycle and period.
2. Derive an equation for the signal's ripple as a function of $R$, $C$, and the PWM signal's duty cycle and period.
3. Assume that the PWM signal has a 50 percent duty cycle, $RC$ is 1 milli-second. Use the preceding equations to plot the ripple and steady state value of the capacitor's voltage as a function of the PWM signal's period, $T$. Use this plot to select a range of periods for which the capacitor's voltage ripple is less than 5 percent. Use the largest value of $T$ ensuring a 5 percent ripple and plot the average capacitor voltage as a function of the PWM signal's duty cycle. What does this plot suggest about the relationship between the duty cycle, $T_1/T$, and the average steady-state capacitor voltage?

4. Before starting the In-lab task, show your pre-lab work to the TA so we can verify the correctness of your analysis and design.