Joseph J. Nahas

Patents

  1. US8184476, J. Nahas, T. Andre, C. Subramanian, “Random access memory architecture including midpoint reference,” 22 May 2012.
  2. US7543211, J. Nahas, T. Andre, C. Subramanian, "Toggle memory burst," 2 June 2009.
  3. US7370260B2, J. Nahas, "MRAM having error correction code circuitry and method therefor," 6 May 2008.
  4. US7292484B1, T. Andre, B. Garni, J. Nahas, "Sense amplifier with multiple bits sharing a common reference," 6 November 2007.
  5. US7280388B2, J. Nahas, "MRAM with a write driver and method therefor," 9 October 2007.
  6. US7266486B2, J. Nahas, "Magnetoresistive random access memory simulation," 4 September 2007.
  7. US7206223B1, J. Nahas, et al., "MRAM memory with residual write field reset," 17 April 2007.
  8. US7154772B2, J Nahas, et al., "MRAM architecture with electrically isolated read and write circuitry," 26 December 2006.
  9. US7082389B2, J. Nahas, "Method and apparatus for simulating a magnetoresistive random access memory (MRAM)," 25 July 2006.
  10. US7012841B1, J. Nahas, "Circuit and method for current pulse compensation," 14 March 2006.
  11. US6944052B2, C. Subramanian, J. Nahas, "Magnetoresistive random access memory (MRAM) cell having a diode with asymmetrical characteristics," 13 September 2005.
  12. US6909631B2, M. Durlam, et al.,"MRAM and methods for reading the MRAM," 21 June 2005.
  13. US6903964B2, J. Nahas, et al., "MRAM architecture with electrically isolated read and write circuitry," 7 June 2005.
  14. US6894937B2, B. Garni, T. Andre, J. Nahas, "Accelerated life test of MRAM cells," 17 May 2005.
  15. US6888743B2, Durlam, et al., "MRAM architecture," 3 May 2005.
  16. US6859388B1, J. Nahas, et al., "Circuit for write field disturbance cancellation in an MRAM and method of operation," 22 February 2005.
  17. US6842365B1, J. Nahas, et al., "Write driver for a magnetoresistive memory," 11 January 2005.
  18. US6760266B2, B. Garni, et al., "Sense amplifier and method for performing a read operation in a MRAM," 6 July 2004
  19. US6744663B2, B. Garni, et al., "Circuit and method for reading a toggle memory cell," 1 June 2004.
  20. US6714442B1, J. Nahas, "MRAM architecture with a grounded write bit line and electrically isolated read bit line," 30 March 2004.
  21. US6714440B2, C. Subramanian, T. Andre, J. Nahas, "Memory architecture with write circuitry and method therefor," 30 March 2004.
  22. US6711068B2, C. Subramanian, et al., "Balanced load memory and method of operation," 23 March 2004.
  23. US6711052B2, C. Subramanian, T. Andre, J. Nahas, "Memory having a precharge circuit and method therefor," 23 March 2004.
  24. US6700814B1, J. Nahas, T. Andre, B. Garni, "Sense amplifier bias circuit for a memory having at least two distinct resistance states," 2 March 2004
  25. US6693824B2, J. Nahas, et al., "Circuit and method of writing a toggle memory," 17 February 2004.
  26. US6667899B1, C. Subramanian, T. Andre, J. Nahas, "Magnetic memory and method of bi-directional write current programming," 23 December 2003.
  27. US6657889B1, C. Subramanian, et al., "Memory having write current ramp rate control," 2 December 2003.
  28. US6621729B1, B. Garni, et al., "Sense amplifier incorporating a symmetric midpoint reference," 16 September 2003.
  29. US6600690B1, J. Nahas, et al., "Sense amplifier for a memory having at least two distinct resistance states," 29 July 2003.
  30. US6580298B1, C. Subramanian, et al., "Three input sense amplifier and method of operation," 17 June 2003.
  31. US6538940B1, J. Nahas, T. Andre, B. Garni, "Method and circuitry for identifying weak bits in an MRAM," 25 March 2003.
  32. US6091287, J. Salter, J. Nahas, W. Martino, "Voltage regulator with automatic accelerated aging circuit," 18 July 2000.
  33. US5614816, J. Nahas, "Low voltage reference circuit and method of operation," 25 March 1997.
  34. US4674114, P. Crouch, J. Nahas, H. Ng, "Fraud prevention in an electronic coin telephone set," 16 June 1987.
  35. US4625078, P. Crouch, J. Nahas, H. Ng, "Fraud prevention in an electronic coin telephone set," 25 November 1986.
  36. US4567325, P. Crouch, J. Nahas, H. Ng, "Controller for a coin telephone set," 28 January 1986.
  37. US4539552, P. Davis, et al., "Digital-to-analog converter," 3 September 1985.
  38. US4357496, J. Nahas, "Keypad logic interface circuit," 2 November 1982.
  39. US4352958, P. Davis, et al., "Electronically-switched multifrequency generator with transducer control," 5 October 1982.
J. Nahas Homepage
Last modified: Tue Dec 11 14:13:17 EST 2012