Dr. Peter M. Kogge

Education

• Ph.D. Electrical Engineering, Stanford University, 1973
• M.S Systems & Engineering Sciences, Syracuse University, 1970
• B.S. Electrical Engineering, University of Notre Dame, 1968

Vitae

Research Interests

While at IBM his group designed the first multi-processor PIM device with significant DRAM memory: the EXECUBE chip which integrated 4 Mbits of DRAM with over 100K gates of logic to implement on a single chip a complete 8 way binary hypercube parallel processor which could run in both SIMD and MIMD modes. He also designed and built the RTAIS parallel processor which demonstrated a pure SIMD PIM-like architecture optimized for supporting a LINDA-like parallel processing model, with real time scheduling included. Prior parallel machines included the IBM 3838 Array Processor which for a time was the fastest single precision floating point processor marketed by IBM, and the Space Shuttle Input/Output Processor which has flown on every Shuttle mission, and probably represents the first true parallel processor to fly in space, and one of the earliest examples of multi-threading architectures. His Ph.D. thesis on the parallel solution of recurrence equations was one of the early works on what is now called parallel prefix operations, and applications of those results are still acknowledged as defining the fastest possible implementations with limited fan-in blocks.

Grants and Funded Research

• Sandia National Labs, "Understanding Performance of New PIM-Based Execution Models," 2/1/03 through 12/31/03.
• DARPA through Cray Inc., "High Productivity Computing Systems," 6/14/02 through 6/30/03. Architectures for trans-Petaflops computers.
• NSF, "NIRT: Architectures and Devices for Quantum Dot Cellular Automata," 7/15/02 through 7/14/06. Fabrication techniques, experiments, and architectures for complex QCA-based systems.
• Semiconductor Research Corp., "Memory Architectures in QCA," 9/1/00 through 8/31/03. Design and characterize memory structures developed from QCA devices.
• DARPA, "Morphable Computer Architectures for Highly Energy Aware Systems," 5/19/00 through 5/18/02. Develop computer architecture where energy/performance characteristics can be shaped to meet available energy profiles, and matching support tools.
• JPL, "Quantum dot Cellular Automata Defect Tolerant Architectures," 9/1/00 through 8/31/03. Definition of fault models in QCA and architectures that handle them.
• JPL, "Phase III HTMT PIM Memory System Design," 1/1/00 to 5/31/01. As part of HTMT petaflops project, to more completely design PIM node architectures to implement multi-level smart memory hierarchy and support alternative execution models.
• DARPA, "DIVA: Data IntensiVe Architecture," 4/98 to 3/01. Joint project with USC/ISI to architect and fabricate a PIM device using leading edge DRAM technology and to construct multi-chip memory systems capable of performing "in-memory" access, search, and processing of irregular data structures for data intensive applications.
• Lockheed Martin, Owego, "System Concepts for PIM Accelerators," 9/1/98 to 8/31/99. Prototype software and applications for EXASPHERE M32R/D based PIM prototype accelerator.
• JPL, "Hybrid Technology MultiThreaded (HTMT) System: PIM Based Memory Hierarchy," 5/23/97 to 12/31/99. Joint multi-university project to architect complete petaflops-level machine capable of deployment in 2007 timeframe.
• Lockheed Martin, Owego, "PIM Prototype System Demonstrator," 9/1/97 to 8/31/98. Construction of EXASPHERE: multi M32R/D based "smart memory" PCI card.
• Extension of JPL Grant No. 960587, "Scalable Spaceborne Computing Using PIM Technology." A PIM chip architecture for deep space applications.
• NSF CDA-9712921, "From Bits to Chips: A Multidisciplinary Curriculum for Microelectronics System Design Education," Sept. 1997 to July 31, 2000. Reworking parts of the undergraduate computer science, computer engineering, and electrical engineering curricula to provide a comprehensive computer design thread that spans from instruction set and compiler issues, through computer organization, to fabrication of complete CMOS microprocessors.
• NSF ACS96-12028, "Point Design for 100 TF PIM-based Computers," Sept. 1, 1996 to August 31, 1997. Architectural studies of potential machines designed with PIM technology to meet 100 TFs in 2004 timeframe.
• JPL Grant No. 960587, "Scalable Spaceborne Computing Using PIM Technology," May 15, 1996 to Nov. 15, 1996. Applicability of PIM technology to potentially satisfy deep space exploration platforms.
• Mayo Foundation/ARPA, "PIM Based Accelerator Technology Infrastructure," May 1, 1996 to May 31, 1997. Identify state of the art in PIM technology and roadblocks to its utilization in accelerators.
• NEC Research Institute, "High Speed Content-based Image Retrieval Techniques," April 1, 1996 to May 31, 1997. Sizing of potential PIM-based image search engines for very large image database problems.
• NASA Grant # NAG5-2998, "Processing-In-Memory Architectures Peta(Fl)ops Computing," July, 1995 to July 1996. Design space for PIM technology that is relevant to possible petaflops level computers.
• NSF Grant #MIP-9503682, "Architectural Techniques for Inherently Low Power Computers," Sept. 1995 to August, 1998. Techniques starting at the instruction set architecture level that allow design of inherently low power computer architectures.

Honors and Awards

• Kaneb Center Teaching Award, 2003
• Outstanding CSE Teacher for 2002, Univ. of Notre Dame, CSE Dept.
• Outstanding CSE Teacher for 1999, Univ. of Notre Dame, CSE Dept.
• Distinguished Visiting Scientist, Jet Propulsion Lab, July 1997
• Daniel Slotnick Award for Most Original Paper, Int. Conf. of Parallel Proc., Aug. 1994
• IBM Fellow, 1993
• 5th Level IBM Invention Plateau, 1992
• IBM FSD President's Award for Patented Parallel Processor Architecture Development, 1991
• IBM Outstanding Innovation Award for AI Parallel Processor, 1990
• IEEE Fellow, 1990
• Elected Member, IBM Academy of Technology, 1990
• IEEE Distinguished Visitor, 1988-1989
• IEEE Senior Member, 1986
• IBM Informal Award, B-1B Computer Performance, 1982
• IBM Informal Award, Military Computer Family, 1981
• Best Paper, 4th International Symposium on Computer Architecture, 1977
• IBM Outstanding Innovation Award, 3838 Array Processor, 1976
• IBM Outstanding Contribution Award, Space Shuttle IOP, 1974
• IBM Informal Award, Space Shuttle Computer, 1973
• IBM Resident Fellowship, Stanford Univ., 1970-1972
• Summa Cum Laude, Univ. of Notre Dame, 1968
• Fr. Steiner Award for Engineering Scholarship, Univ. of Notre Dame, 1968

Professional Societies: IEEE, ACM, AAAI, ASEE

Books and Proceedings

1. with Craig S. Lent, et al, "Quantum-dot Cellular Automata," Book Chapter.
2. Kogge, Peter M., Editor, Special Issue on Federal Systems, IBM Journal of Research and Development, March, 1994.
3. Kogge, Peter M., The Architecture of Symbolic Computers, McGraw Hill, NY, 1990
4. Kogge, Peter M., Editor, Proc. of 1988 Int. Conf. on Parallel Processing, Vol. I, II, and III, Penn State Univ. Press, Aug. 1988
5. Kogge, Peter M., Apxntektypa Kohbenephhbix EBM, Russian language translation of The Architecture of Pipelined Computers, Radio Moscow, 1985
6. Kogge, Peter M., The Architecture of Pipelined Computers, McGraw Hill, NY, 1981

Patents and Disclosures

1. Wilkinson, Paul Amba, Dieffenderfer, James Warren, Kogge, Peter M., R. R. Richardson, D. M. Lesmeister, V. J. Smoral, "Controller for a SIMD/MIMD Array Having an Instruction Sequencer Utilizing a Canned Routine Library," US Patent 5,765,012, issued 6/09/98
2. Wilkinson, Paul Amba, Dieffenderfer, James Warren, Kogge, Peter M., and Nicholas Jerome Schoonover, "Autonomous SIMD/MIMD processor memory elements," US Patent 5,717,944, issued 2/10/98
3. Barker, Thomas Norman, Kogge, Peter M., et al , "Advanced parallel array processor (APAP)," US Patent 5,717,943, issued 2/10/98
4. Wilkinson, Paul Amba, Dieffenderfer, James Warren, Kogge, Peter M., and Nicholas Jerome Schoonover, "Slide bus communications functions for SIMD/MIMD array processor," US Patent 5,713,037, issued 1/27/98
5. Barker, Thomas Norman, Kogge, Peter M., et al., "Advanced parallel array processor (APAP)," US Patent 5,710,935, issued 1/20/98
6. Wilkinson, Paul Amba, Dieffenderfer, James Warren, Kogge, Peter M., and Nicholas Jerome Schoonover, " SIMD/MIMD inter-processor communication," US Patent 5,708,836, issued 1/13/98
7. Olnowich, Howard Thomas, Barker, Thomas Norman, Kogge, Peter M., and Gilbert Clyde Vandling III, "Priority broadcast and multi-cast for unbuffered multi-stage networks," US Patent 5,680,402, issued 10/21/97
8. Wilkinson, Paul Amba and Kogge, Peter M., "Array processor dotted communication network based on H-Dots," US Patent 5,630,162, issued 4/27/95
9. Bezek, John D. and Kogge, Peter M., " Method for interfacing applications with a content addressable memory," US Patent 5,615,360, issued 3/25/97
10. Bezek, John D. and Kogge, Peter M., " Inferencing production control computer system," US Patent 5,615,309, issued 3/25/97
11. Smoral, Vincent J. Kogge, Peter M., and Sementille, Phillip J., " Hybrid Architecture for Video On Demand Servers," US Patent 5,608,448, issued 3/4/97
12. Barker, Thomas Norman, Kogge, Peter M., et al , "Advanced parallel array processor (APAP)," US Patent 5,590,345, issued 12/31/96
13. Bezek, John D. and Kogge, Peter M., "Refraction algorithm for production systems with content addressable memory," US Patent 5,579,441, issued 11/26/96
14. Bezek, John D. and Kogge, Peter M., "Inferenceing production control computer system," US Patent 5,517,642, issued 5/14/96
15. Kogge, Peter M., "Dynamic multi-mode parallel processing array," US Patent 5,475,856, issued 12/12/95
16. Brodnax, Timothy B., Bullis, Bryan K., King, Steven A., Kogge, Peter M., and Dale A. Rickard, "Data processing system having prediction by using an embedded guess bit of remapped and compressed opcodes," US Patent 5,463,746, issued 10/31/95
17. Olnowich, Howard T., Barker, Thomas N., Kogge, Peter M., and Gilbert Clyde Vandling III, "Dual priority switching apparatus for simplex networks," US Patent 5,444,705, issued 8/22/95
18. Kogge, Peter M., G. Vandling, L.A. Watson, E.W. Buterbaugh, H.T. Olnowich, "Hiding of Store Protection Checks in a Pipelined Computer," Published in IBM Tech. Disc. Bulletin, 5/92
19. Kogge, Peter M., T.W. Giambra, W. Land, Jr, "Hybrid Artificial Neural System (ANS)/Expert System," Published in IBM Tech. Disc. Bulletin, 6/90
20. Kogge, Peter M., K.T. Truong, D.A. Rickard, R.L. Schoenike, "Checkpoint Retry Mechanism," US Patent 4,912,707, issued 3/27/90
21. Kogge, Peter M., "Skewed Matrix Address Generator," US Patent #4,370,732, issued 1/25/83
22. Kogge, Peter M., "Data Communication Bus Structure," US Patent # 4,085,448, issued 4/18/78
23. Kogge, Peter M., "Program Pipeline Recurrence Problem," Published IBM Tech. Disc. Bulletin, 12/73

Refereed Articles

1. Sarah Frost, Arun Rodrigues, Charles Giefer, and Peter M. Kogge, "Bouncing Threads: Merging a new execution model into a nanotechnology memory," IEEE Annual Symp. on VLSI, Feb. 20-21, 2003.
2. Dmitry Ponomarev, Gurhan Kucuk, Oguz Ergin, Kanad Ghose, Peter Kogge, "Energy-Efficient Issue Queue Design" To appear in IEEE Transactions on Very Large Scale Integration Systems, 2003.
3. Gary E. Bernstein, Jay B. Brockman, Gregory L. Snider, Peter M. Kogge, and Barbara E. Walvoord, "From Bits to Chips: A Multidisciplinary Curriculum for Microelectronic System Design Education," Midwest Conf. of ASEE, April 12, 2002.
4. Michael T. Niemier and Peter M. Kogge, "Exploring and Exploiting Wire-Level Pipelining in Emerging Technologies" (ps), International Symposium of Computer Architecture, Sweden, July 2001. pp. 166-177
5. Gurhan Kucuk, Kanad Ghose, Dmitry Ponomarev, Peter Kogge, "Energy Efficient Instruction Dispatch Buffer Design for Superscalar Instruction Dispatch Buffer Design for Superscalar Processors," Proc. ACM Int. Symp. on Low Power Electronics and Design 2001 (ISLPED01), pp. 237-243.
6. Zyuban, Victor and Peter M. Kogge, "Inherently Lower-Power High-Performance Superscalar Architectures," IEEE Trans. on Computers, March 2001
7. Niemier, Michael T. and Peter M. Kogge, "Problems in designing with QCAs: Layout = Timing," Int. J. of Circuit Theory and Applications, 4 January 2001, Vol. 29, pp. 49-62.
8. Murphy, Richard, and Peter M. Kogge, "The Characterization of Data Intensive Memory Workloads on Distributed PIM Systems," Intelligent Memory Systems Workshop, ASPLOS-IX 2000, Boston, MA, Nov. 12, 2000.
9. Kudriavtsev, Alexei, and Peter M. Kogge, "SMT Possibilities for Decoupled Architectures," Memory access decoupling for superscalar and multiple issue Architectures (MEDEA) Workshop, Int. Conf. on Parallel Architectures and Compilation Techniques, Philadelphia, PA, Oct. 19, 2000.
10. Zyuban, Victor and Peter M. Kogge, "Optimization of High-Performance Super-Scalar Architectures for Energy-Delay Product," ACM/IEEE International Symposium on Low Power Electronics and Design, July 2000, Portofino, Italy
11. Yerosheva, Lilia and Peter M. Kogge, "Prototyping HTMT Execution Model Using Petri Nets," World Multiconference on Systemics, Cybernetics and Informatics, July 23-26, 2000, pp.318-323.
12. Hall, Mary, Peter Kogge, Jeff Koller, Pedro Diniz, Jacqueline Chame, Jeff Draper, Jeff LaCoss, John Granacki, Apoorv Srivastava, William Athas, Jay Brockman, Vincent Freeh, Joonseok Park, Jaewook Shin. "Mapping Irregular Applications to DIVA, A PIM-based Data-Intensive Architecture," Supercomputing, Portland, OR, Nov. 1999.
13. Ghose, Kanad, Kiran R. Desai, Peter M. Kogge. "Accelerating object-oriented applications using method lookup caches and register windowing," J. of Systems Arch., Vol. 45, 1999, pp. 1023-1046.
14. Niemier, Michael and Peter M. Kogge, "Logic in Wire: Using Quantum Dots to Implement a Microprocessor," Int. Conf. on Electronics, Circuits and Systems (ICECS '99), Cyprus, Sept. 1999
15. Brockman, Jay B., Peter, M. Kogge, Vincent Freeh, and Thomas Sterling, "Microservers: A New Memory Semantics for Massively Parallel Computing," Int. Conf. on Supercomputing, Rhodes, Greece, June 20-25, 1999, pp. 454-463.
16. Niemier, Michael and Peter M. Kogge, "Designing Complex Logic Systems with QCA Devices," Great Lakes Symposium on VLSI, Ann Arbor MI, March 2-4, 1999.
17. Zyuban, Victor and Peter M. Kogge, "Application of STD Method to Latch Power Estimates," IEEE Trans. on VLSI Systems, Vol. 7, No. 1, March 1999, pp.111-115
18. Yerosheva (Suslov), Lilia and Peter M. Kogge, "Prototyping Execution Models for HTMT Petaflops Machine in Java," 3rd Workshop on Communications, Architecture, and Applications for Network-based Parallel Computing, in conjunction with 5th Int. Symp. on High Performance Computer Architecture, Orlando, FL, Jan. 9-13, 1999.
19. Zyuban, Victor and Peter M. Kogge, "The Energy Complexity of Register Files," Int. Symp. on Low-Power Electronics and Design, Monterey, CA, Aug. 10-13, 1998, pp.305-310.
20. Kogge, Peter M., Jay B. Brockman, Vincent Freeh, "Processing-In-Memory Based Systems: Performance Evaluation Considerations," Workshop on Performance Analysis and its Impact on Design - PAID'98, held in conjunction with Int. Symp. on Computer Arch., Barcelona, Spain, June 27-28, 1998.
21. Zyuban, Victor and Peter M. Kogge, "Split Register File Architecture for Inherently Lower Power Architectures," Workshop on Power-Driven Microarchitecture, held in conjunction with Int. Symp. on Computer Arch., Barcelona, Spain, June 27-28, 1998.
22. Zawodny, Jason T., Jay B. Brockman, Peter M. Kogge, Eric Johnson, "Cache-In-Memory: A Lower Power Alternative," Workshop on Power-Driven Microarchitecture, held in conjunction with Int. Symp. on Computer Arch., Barcelona, Spain, June 27-28, 1998.
23. Sterling, Thomas and Peter M. Kogge, "An Advanced PIM Architecture for Spaceborne Computing," 1998 IEEE Aerospace Conf. Proc., March 21-28, 1998.
24. Daescu, Ovidiu, Peter M. Kogge, and Danny Chen, "Parallel Content-Based Image Analysis on PIM Processors," IEEE Workshop on Content-Based Access to Image and Video Databases, June 21, 1998.
25. Tian, Yi, Edwin H.M Sha, Chantana Chantrapornchai, and Peter M. Kogge, "Optimizing Data Scheduling on Processor-In-Memory Arrays," to be presented at IPPS'98, Orlando, FL, March 30 - April 3, 1998.
26. Nanayanaswamy, Lakshmi and Peter M. Kogge, "Combinators-In-Memory: An Unconventional Approach to Avoiding the Memory Wall," 1st Int. Conf. on Unconventional Models of Computation, Auckland, NZ, Jan. 5-8, 1998.
27. Tian, Yi, Edwin Sha, Chantana Chantrapornchai, and Peter M. Kogge, "Efficient Data Placement for Processor-In-Memory Array Processors," 9th Int. Conf. on Parallel and Dist. Computing and Systems, Washington D.C., Oct. 13-16, 1997.
28. Surma, David, Edwin Hsing-Mean Sha, and Peter M. Kogge, " SCORE: An Efficient Technoque to Reduce Congestion in Parallel Systems," 10th Int. Conf. on Parallel and Dist. Computing Systems, New Orleans, LA, Oct. 1-3, 1997.
29. Sheliga, M., E. Sha, Peter M. Kogge, "Compression Using the EXECUBE Processor Array," IEEE National Aerospace and Electronics Conference, Dayton, OH, July 14-18, 1997.
30. Kogge, Peter M., S. C. Bass, J. B. Brockman, D. Z. Chen, E, H. Sha, "Pursuing a Petaflop: Point designs for 100TF Computers Using PIM Technologies," 6th Symp. on Frontiers of Massively Parallel Computation, Annapolis, MD, Oct. 25-31, 1996
31. T. Sunaga, Peter M. Kogge, et al, "A Processor In Memory Chip for Massively Parallel Embedded Applicatiions," IEEE J. of Solid State Circuits, Oct. 1996, pp. 1556-1559.
32. Ghose, Kanad, Kiran R. Desai, and Peter M. Kogge, "Using Method Lookup Caches and Register Windowing to Speed Up Dynamically-Bound Object-Oriented Applications," Proc. 22nd Euromicro, pp.441-448, Sept. 1996
33. Brockman, Jay, S. Batill, J. Renaud, J. Kantor, D. Kirkner, Peter M. Kogge, R. Stevenson, "Development of a Multidisciplinary Engineering Design Laboratory at the University of Notre Dame," Proc. ASEE Annual Conf., Wash. D.C., June 23-26, 1996,
34. Kogge, Peter M., T. Giambra, H. Sasnowitz, "RTAIS: An Embedded Parallel Processor for Real-time Decision Aiding," 1995 NAECON, Dayton, OH, March, 1995
35. Kogge, Peter M., T. Sunaga, E. Retter, et al, "Combined DRAM and Logic Chip for Massively Parallel Applications," 16th IEEE Conf. on Advanced Research in VLSI, Raleigh, NC, IEEE Computer Society Press # PR07047 , March 1995, pp. 4-16
36. Kogge, Peter M., "The EXECUBE Approach to Massively Parallel Processing," 1994 Int. Conf. on Parallel Processing, Chicago, IL, August, 1994.
37. Kogge, Peter M., "Declarative Computing: A Technology Driver," Architectektur von Rechensystemem, Springer Verlag, pp. 1-17, 1992.
38. Kogge, Peter M., et al, Avionics Artificial Intelligence (AI) Processor Definition, USAF Wright Labs Report WRDC-TR-1089, Sept., 1990
39. Kogge, Peter M., J. Oldfield, et al, "VLSI and Rules Based Systems," Chap. 4.1 of VLSI for Artificial Intelligence, ed. J.G. Delgado Frias and W. R. Moore, Kluwer Academic Press, 1990
40. Kogge, Peter M., "Function Based Computing and Parallelism: A Review," Parallel Computing, Vol. 2, No. 3, Nov. 1985
41. Kogge, Peter M., "An Architectural Trail to Threaded Code Systems," IEEE Computer, March, 1982
42. Kogge, Peter M., "Algorithm Development for Pipelined Processors," Int. Conf. on Parallel Processing, Bellaire, MI, Aug. 1977
43. Kogge, Peter M., "The Microprogramming of Pipelined Processors," 4th Int. Symp. on Computer Arch., Silver Spring, MD, March 1977
44. Kogge, Peter M., "Parallel Algorithms for the Efficient Solution of Recurrence Problems," IBM J. of R&D, March 1974
45. Kogge, Peter M., "Parallel Algorithms for the Efficient Solution of Recurrence Problems," (shortened version of above), 7th Annual Princeton Conf. on Info. Sciences and Systems, March 1973
46. Kogge, Peter M., "Maximal Rate Pipelined Solutions to Recurrence Problems," 1st Annual Symp. on Comp. Arch., Gainsville, FL, Dec. 1973
47. Kogge, Peter M. and H.S. Stone, "A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations," IEEE Trans. on Computers, Aug., 1973

Presentations, Workshops, Unreferreed or Abstract referred Conference Articles, and Invited Talks and Articles

1. Peter M. Kogge,Jeffrey Nankung, Nazeeh Aranki, N. Benny Toomarian, Kanad Ghose, "Characterization of Future Deep Space Computing Loads," accepted for Space Mission Challenges for Information Technology (SMC-IT), Pasadena, CA, July, 2003.
2. Peter M. Kogge, Invited Keynote Speech, "The State of State," HPCA09, Anaheim, CA, Feb. 12, 2003.
3. Peter M. Kogge, Arun Rodriguez, Jeffrey Nankung, Nazeeh Aranki, N. Benny Toomarian, "A Comparative Analysis of Power and Energy Management Techniques in Real Embedded Applications, 6th International Workshop on Innovative Architectures (IWIA'03), Kauai, HI, Jan. 27-29, 2003.
4. Robert J. Minerick, Vincent W. Freeh, and Peter M. Kogge, "Dynamic power management using feedback." Proc. of Workshop on Compilers and Operating Systems for Low Power, pp. 6-1 to 6-10, Charlottesville, Va, September, 2002.
5. Peter M. Kogge, "The Future of Computing," Invited talk at Lawrence Livermore National Lab's, Physics and Advanced Technologies Directorate, PAT Luminaries Day in conjunction with LLNL's 50th anniversary, June 28, 2002. Also at Sandia National Labs, Oct. 29, 2002.
6. Sarah Elizabeth Frost, Arun F. Rodrigues, Andrew W. Janiszewski, Randal T. Rausch, and Peter M. Kogge "Memory in Motion: A Study of Storage Structures in QCA." 1st Workshop on Non-Silicon Computation (NSC-1), held in conjunction with 8th Int. Symp. on High Performance Computer Architecture (HPCA-8), Boston, MS. Feb. 3, 2002.
7. Michael T. Niemier, Arun F. Rodrigues, and Peter M. Kogge "A Potentially Implementable FPGA for Quantum Dot Cellular Automata," , 1st Workshop on Non-Silicon Computation (NSC-1), held in conjunction with 8th Int. Symp. on High Performance Computer Architecture (HPCA-8), Boston, MS. Feb. 3, 2002.
8. Michael G. Kirkpatrick Vincent W. Freeh Peter M. Kogge Robert J. Minerick, "Exploiting Morphable Microarchitectures for Saving Energy," Univ. of Notre Dame CSE Dept. Tech. Report, 0109, Aug. 22, 2001.
9. Murphy, Richard and Peter M. Kogge. "Trading Bandwidth for Latency: Managing Continuations through a Carpet Bag Cache," Int. Workshop on Innovative Arch., Kona, HI, Jan. 12-13, 2002.
10. Zawodny, Jason and Peter M. Kogge, "Cache In Memory," International Workshop on Innovative Architecture 2001 (IWIA01), Maui High Performance Computer Center, Maui, HI, Jan. 18-19, 2001.
11. Kogge, Peter M., Vincent W. Freeh, Kanad Ghose, Nikzad Toomarian, Nazeeh Aranki, "Morph: Adding an Energy Gear to a High Performance Microarchitecture for Embedded Applications," Kool Chips Workshop, MICRO-33, Monterey, CA, Dec. 10, 2000
12. Ghose, Kanad, Dmitry Ponomarev, Gurhan Kuck, Andrew Flinders, Peter M. Kogge, "Exploiting Bit-Slice Inactivities for Reducing Energy Requirements of Superscalar Processors," Kool Chips Workshop, MICRO-33, Monterey, CA, Dec. 10, 2000
13. Niemier, Michael, and Peter M. Kogge, "Quantum Cellular Automata," Nanotech 2000, Dallas, TX, Sept. 27, 2000
14. Guest on Milton Friedman Show on WGN Radio, Chicago, on 4/29/00, on topic of nanotechnology.
15. Kogge, Peter M., "PIM Architectures to Support Petaflops Level Computation in the HTMT Machine," 3rd Int. Workshop on Innovative Architectures, Maui High Performance Computer Center, Maui, HI, Nov. 1-3, 1999.
16. Niemier, Michael T., Peter M. Kogge. "Designing a Microprocessor using Quantum Cellular Automata (QCA), Poster at
17. Kogge, Peter M., "In Pursuit of a Petaflop: Overcoming the Bandwidth/Latency Wall," 10th Annual Workshop on Interconnections within High-Speed Digital Systems, 9-12 May 1999, Hilton of Santa Fe, Santa Fe, NM
18. Niemier, Michael and Peter M. Kogge, "Logic in Wire: Using Quantum Dots to implement Really Dense Logic," Proc. Third Petaflop Workshop, associated with Frontiers of Massively Parallel Processing, Annapolis, MD, Feb. 22, 1999.
19. Kogge, Peter M., "Redefining Memory," Stanford University, Nov. 16, 1998.
20. Kogge, Peter M., Jay B. Brockman, Robert Ferraro, Eric Mjolsness, Paul S. Kapcio, Joseph R. Marshall, "Use of Processing-In-Memory (PIM) Technology to Enable On-Site "Geologist's Assistant" Processing," NASA JPL Mars Micromission Workshop, Pasadena, CA, May 21-22, 1998, pp.44-45.
21. Kogge, Peter M., "Processing In Memory: A Technology for Scalable Computing," Invited talk, NSF Workshop on 500 Million Transistor Chips, Princeton University, Princeton, NJ., March 11-12, 1998.
22. Kogge, Peter M., Jay B. Brockman, Thomas Sterling, and Guang Gao, " Processing-In-Memory: Chips to Petaflops," IRAM Workshop, Int. Symp. on Computer Arch., Denver, CO, June 1, 1997, paper and presentation.
23. Kogge, Peter M., and Jay B. Brockman, "Processing-In-Memory (PIM): Capabilities and Opportunities for Deep Space Systems," CISM Workshop on X2000 Deep Space Processing, JPL, Pasadena, CA, June 3, 1997.
24. Kogge, Peter M., Jay B. Brockman, Vincent Freeh, Steven C. Bass, "Petaflops, Algorithms, and PIMs," 1997 Petaflops Algorithm Workshop (PAL'97), Williamsburg, VA, April 13-18, 1997, paper and presentation.
25. Kogge, Peter M. invited panelist Petaflops Computing session, topic: "PIMs and Petaflops", 1996 Supercomputing Conf., Nov. 22, 1996, Pittsburgh, PA
26. Kogge, Peter M., "Procesor-In-Memory Based Architectures for Very High Performance MPP Computing," invited talk IBM Workshop on Performance Analysis and its Impact on Design, on opening of IBM VLSI Research Lab, Austin, TX, March 27, 1996, also Univ. of California, Berkeley, ECE Dept., April 8, 1996
27. Kogge, Peter M., "Procesor-In-Memory Based Architectures for Petaflops MPP Computing," 1995 NSF-NASA Workshop on Petaflops Applications, Bodega Bay, CA, Aug. 18-22, 1995, also NEC Reseach Labs, Princeton, NJ, Oct. 1995
28. Invited Participant, NASA/JPL Workshop on Microspacecraft, Feb. 1995
29. Kogge, Peter M., "Computing Post 2007 - the Peta(Fl)ops Challenge," IBM T.J. Watson Research Center, Feb. 7, 1995. Also to Purdue Univ. ECE Dept., Jan. 31, 1995.
30. Kogge, Peter M., "Processors-In-Memory (PIM) Chip Architectures for Peta(FL)ops Computing," Peta(FL)ops Workshop as part of 1995 Frontiers in Computing, Va., Feb. 6, 1995.
31. Kogge, Peter M., " Peta(Fl)ops Computer Architectures," JASON Group, San Diego, CA, June 1994
32. Invited Participant, Caltech Workshop on Peta(fl)op Processing, Pasadena, CA Feb., 1994
33. Kogge, Peter M., "The EXECUBE Approach to Massively Parallel Processing," Distinguished. Lecturer Talk, Univ. of Southern Ca., Sept. 1993, also Univ. of Washington, Sept. 1993, also Univ. of Notre Dame, Oct. 1993, also Univ. of Utah, Jan. 1994, also Binghamton Univ., Feb. 1994.
34. Kogge, Peter M. ., "EXECUBE and Synthetic Aperture Radar," JASON Group, San Diego, June 1993.
35. Kogge, Peter M., "An Introduction to AI," AIAA Aerospace Conf., Reno, NV, Jan. 1993
36. Kogge, Peter M. Seminar series on "Declarative Computing: A Different Path to Harnessing the Power of Parallelism," 1st School of High Performance Scientific Computation, Rio de Janeiro, Brazil, Aug. 1992, also AIAA Aerospace Sciences Conf., Reno, NV, Jan. 1994
37. Kogge, Peter M. and K. Ghose, Tutorial on "Pipelining and Fine Grain Parallelism," 21st Int. Conf, on Parallel Processing, Chicago, IL, Aug. 1992
38. Kogge, Peter M. and K. Ghose, Tutorial on "Pipelining: Parallelism in the Small," 19th Int. Symp. on Computer Arch., Gold Coast, Australia, May 1992
39. Kogge, Peter M., Tutorial on "Declarative Computing," 19th Int. Symp. on Computer Arch., Gold Coast, Australia, May 1992
40. Kogge, Peter M., J. Mastranadi and T. Giambra, "The Real Time Artificial Intelligence System," NAECON, Dayton, OH, May 1992
41. Kogge, Peter M., "Declarative Computing: A Technology Driver," Opening Address for 1992 German National Computer Conference, Kiel, Germany, March 1992.
42. Kogge, Peter M., "Content Addressable Memories," NAECON, Dayton OH, May 1991, also Univ. of Notre Dame, Sept. 1991, also Univ. of Utah, Oct. 1989
43. Kogge, Peter M., "AI Programming Paradigms," USAF STSC Joint Software Conference, Salt Lake City, Utah, April 1991
44. Kogge, Peter M., M. Robinson, T. Giambra, "Distributed Intelligent Defensive System," AIAA Aerospace Conf., Jan 1989, also DARPA Workshop on Requirements for Real Time Avionics Processors for Artificial Intelligence, Monterey, CA, Sept. 1989
45. Kogge, Peter M. IEEE Distinguished Lecturer Series, "Compiling Parallel Logic Programs," and "Functional Languages and Parallelism," IEEE Society of Orlando, Orlando, FL, Jan. 1990, also Univ. of South Florida, Orlando, FL, Jan. 1990, also Univ. of Southwest Louisiana, Lafayette, LA, Jan. 1989, also Georgia Tech., Atlanta, GA, Jan. 1989, also Iowa State Univ., Ames, IA, March 1988, also Cornell Univ., Ithaca, NY, Feb. 1988
46. Kogge, Peter M., "VLSI and Rules Based Systems, " 1988 International Workshop on VLSI for AI, Oxford, England, July 1988, also IBM ITL on Expert Systems, Yorktown Heights, NY Oct. 1988, also Technical Vitality Series Talk, IBM Rochester, Dec. 1988
47. Kogge, Peter M., "Avionics, AI, and Embedded Processing Systems," AIAA Computers in Aerospace VI, Boston, MA, Oct. 7, pp. 236-245, 1987
48. Kogge, Peter M., "The FSD Owego Artificial Intelligence Laboratory," IBM FSD Technical Directions, Vol. 12, No. 3 and 4, pp. 13-16, 1986
49. Kogge, Peter M., "High Performance Inference Processing," IBM FSD Technical Directions, Vol. 12, No 3 and 4, pp. 17-21, 1986
50. Kogge, Peter M., "AI and Scientific Computing: Are They Compatible?," Panel Session at Int. Session on Computer Arch., Tokyo, Japan, May, 1986
51. Kogge, Peter M., "Artificial Intelligence," Guthrie Medical Center, Guthrie, PA, Feb. 1986
52. Kogge, Peter M., "How Inference Engines Really Work," IBM FSD Conf. on AI, Gaithersburg, MD, June 1985, also ARTWG meeting, Ft. Worth, TX, Oct. 1986, also SUNY Binghamton CS Lecture Series, March 1987
53. Kogge, Peter M., "Function Based Computing and Parallelism," SHARE European Group Spring Meeting, Eindoven, Netherlands, April, 1985
54. Kogge, Peter M., "Advanced Processing System," IBM FSD Technical Symp., Rockville, MD, Sept. 1984
55. Kogge, Peter M., "Pipelined Processing," New York Univ., May 1984, also IBM Europe Institute, Davos, Switzerland, July, 1984, also AIAA von Neumann Computer Workshop, Nassau, TX, Oct. 1984
56. Kogge, Peter M., "Functional Languages and Parallelism," IBM Europe Institute, Davos, Switzerland, July, 1984
57. Kogge, Peter M., "Standard ISAs and VLSI - Two Interacting Trends," 2nd AFSC Standardization Conf., Dayton, OH, Nov. 29, 1982
58. Kogge, Peter M., "On Removing the Magic from FORTH," invited keynote speech, 3rd Annual FORTH Conference, San Jose, CA, Oct. 1982
59. Kogge, Peter M., "Timing, Control, and Performance - Scheduling Activities on a Pipeline," MIT, Cambridge, MA, April, 1982
60. Kogge, Peter M. and P. Olsen, "The Army's MIL-STD-1862 and the Military Computer Family," IBM FSD Technical Directions, Vol. 7, No. 2, Summer, 1981
61. Kogge, Peter M., "Development Methodology for Pipelined Algorithms," IBM Symp. on Math and Computation, Watson Research Center, Yorktown Heights, NY, Sept., 1976

Technical Reports

1. Daescu, Ovidiu, Peter M. Kogge, and Danny Z. Chen, "Parallel Content Based Image Analysis on PIM Processors," Notre Dame CSE TR-9710, Sept. 15, 1997.
2. Kendall, Richard, John A. Morelli, Vincent W. Freeh, and Peter M. Kogge, "Computation with Memory Using Transforms," Notre Dame CSE TR-9707, July 15, 1997.
3. Brockman, Jay B., and Peter M. Kogge, "The Case for PIM," Notre Dame CSE TR-9707, Jan. 10, 1997.
4. Kogge, Peter M and Robert Szczerba, "Final Report: Scalable Spaceborne Computing Using PIM Technology," Notre Dame CSE TR-9632, Nov. 14, 1996.
5. Szczerba, Robert and Peter M. Kogge, "A New Generation of Path Planning Algorithms for Planetary Exploration based on the Shamrock Architecture," Notre Dame CSE TR-9631, Nov. 14, 1996.
6. Kogge, Peter M. Final Report: Processor-In-Memory (PIM) Based Architectures for Petaflops Potential Massively Parallel Processing, Notre Dame CSE TR-9626, Sept. 1996
7. Zyuban, V. and Peter M. Kogge, Transition Graph Methodology for Estimating Power Dissipation and Its Application to Latch Design, Notre Dame CSE TR-9624, Sept. 1996
8. Kogge, T. Giambra and H. Sasnowitz, RTAIS Contract Final Report, March 1994.
9. Kogge, Peter M. SRS for the Extended QUery Interface Library (EQUIL), "IBM Owego C93-91-125, June 1992
10. Kogge, Peter M., SRS for the ACP Interface Package, IBM Owego C93-91-116, June 1992
11. Kogge, Peter M., IRS for the ACP Microinstruction Set Architecture, IBM Owego C93-91-119, Jan., 1992
12. Kogge, Peter M., IRS for the ACP Command Chain Instruction Set Interface, Jan. 1992
13. Giambra, T., and Peter M. Kogge, Benchmark Evaluation Results for RTAIS, IBM Owego C93-91-124, Oct. 1991
14. Kogge, Peter M., Associative CoProcessor (ACP) Module Spec. for RTAIS, IBM Owego C93-91-101, March 1991
15. Kogge, Peter M., Shared Memory Module (SMM) Spec. for RTAIS, IBM Owego C93-91-101, March 1992
16. Kogge, Peter M., Processor Module (PM) Spec. for RTAIS, IBM Owego C93-91-103, March 1991
17. Kogge, Peter M., System Segment Spec. for RTAIS, IBM Owego C93-91-104, March 1991
18. Kogge, Peter M., Interface Spec. for RTAIS, IBM Owego C93-91-105, March 1991
19. Kogge, Peter M., A Data Flow Driven CPU, IBM Owego 79-D68-003, Aug. 1979
20. Kogge, Peter M., The Implementation of Winograd Transforms, IBM Owego 78-M83-001, Aug. 1978
21. Kogge, Peter M., IBM 3838 Reservoir Modeling Set Functional Characteristics, IBM GA24-3716-0, File No. S370-08, IBM Corp., Endicott, NY, 1978
22. Kogge, Peter M., A Solution to the Corner Turning Problem, IBM Owego 77-M83-001, Sept. 1977
23. Kogge, Peter M., Array Processor Algorithm Precision Analysis, IBM Owego, Nov. 1976
24. Kogge, Peter M., Array Processor Algorithm Implementation Interface Spec., IBM Owego, July 1976
25. Kogge, Peter M., Gusher Subunit Functional Specification Arithmetic Processor Microlevel Functional Description, IBM Owego, March 1976
26. Kogge, Peter M., A Summary of Division by Multiplication, IBM Owego 75-559-007, April, 1975
27. Kogge, Peter M., A Formal Definition of Object Evaluation and Usage in the System/Intermediate Language Machine (S/ILM), IBM Owego 75-559004, Feb. 1975
28. Kogge, Peter M., Space Shuttle Advanced System/4 PI Prototype IOP Principles of Operation for Bus Control Element (BCE), IBM Owego 6246556, Dec. 1974
29. Kogge, Peter M., Space Shuttle Advanced System / 4 PI Prototype IOP Principles of Operation for Master Sequence Controller (MSC), IBM Owego 6246556, Dec. 1974
30. Kogge, Peter M., IBM System/4 PI Input/Output Processor Microarchitecture Principles of Operations, IBM Owego, Dec. 1974
31. Kogge, Peter M., Analysis of the 1 1/2 Look Algorithm, IBM Owego 74-A31-007, July 1974
32. Kogge, Peter M., Concurrency Simulation Study - Space Shuttle IOP, IBM Owego 74-A31-008, July, 1974
33. Kogge, Peter M., The Theory, Use, and Implementation of CORDIC Algorithms, IBM Owego, 73-559-012, Sept. 1973
34. Kogge, Peter M., A Fault Tolerant Bus, IBM Owego 73-559-008, July, 1973
35. Kogge, Peter M., R. Carberry, R. Bryant, K. Stuart, R. Sixberry, Study of AADC RAM I/O, IBM Owego 73-559-003, April 1973
36. Kogge, Peter M., Minimal Parallelism in the Solution of Recurrence Problems," Stanford Univ. Report SEL-72-044, Sept., 1972
37. Kogge, Peter M., "The Numerical Stability of Parallel Algorithms for Solving Recurrence Problems," Stanford Univ. Report SEL-72-043, Sept. 1973
38. Kogge, Peter M., "A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Problems," Stanford Univ. Report SEL-72-025, March 1972

Professional Activities

• Elected representative from Engineering to Graduate Council, 2002-2003
• Program Committee, ISSCC, 2003.
• Program Co-Chair, 12th Great Lakes Symposium on VLSI, NYC, March 2002
• Program Committee, The 2nd Workshop on Intelligent Memory Systems, ASPLOS 2000
• Architecture Program Committee, Supercomputing Conference, 1998, 1999, 2000, 2002, 2003
• Program Committee, Int. Symp. on Low Power Electronic Design (ISLPED), 2001, 2002, 2003
• Program Vice-Chair, 7th Symposium on the Frontiers of Massively Parallel Computation, Feb. 1999
• Program Chair, 6th Symposium on the Frontiers of Massively Parallel Computation, Oct. 1996
• Member, Program Committee, Petaflops Software Workshop, Bodega Bay, CA, June 1996
• Co-Chair, Petaflops Architecture Workshop, Mandely Beach, CA, April 1996
• Member, Program Committee, Int. Conf. Supercomputing, Phila., PA, 1996, 2003
• Member, Program Committee Int. Symp. Computer Arch., 1994, 1999
• Member, AIAA Committee on Real Time Artificial Intelligence, 1992 to 1994
• Member, Industrial Research Fellows Affiliates, 10/92
• Member, NSF Computer and Computation Research Advisory Board, 1991-1992
• Member, Program Committee, 1990 Workshop on VLSI and AI, Oxford Univ., 1990
• General Technical Chairman, 1989 Int. Conf. on Parallel Processing, 1989
• IEEE Distinguished Visitor, 1988-1990
• Assoc. Editor, IEEE Transactions on Computers, 1986-1989
• Member, Program Committee, IEEE Symp. on Logic Programming, 1989
• Member, External Research Advisory Group, NY State Center for Software and Computer Applications, (CASE Center at Syracuse Univ.), 1988 to 1994
• Member, Program Committee for Fault Tolerant Computing IBM ITL
• Member, Program Committee, IEEE Symp. on Logic Programming, 1988
• Member, Program Committee, Int. Symp. on Computer Arch., 1986
• Member, Faculty Search Committee, SUNY Binghamton, 9/83-9/84

Courses Taught at Notre Dame

• EG111 Introduction to Engineering Systems, Fall 02.
• CSE 210: Discrete Math, Sp 95, 96
• CSE 321: Computer Architecture I, Fa 95
• CSE 322: Computer Architecture II, Sp 97, 98, 99, 00, 01, 02, 03
• CSE 346: Database Concepts, Sp 96
• CSE 411: Automata, Fa 01
• CSE 466, 566: Computer Graphics, Fa 97
• CSE 431, 531: Programming Languages, Fa 94, 96, 98, 99, 03
• CSE 498: Future Trends in Microsystems: Sp 00, 01, 02
• CSE 498A/598A: Survey of Advanced Computer Architectures: Fa 00
• CSE 498I: Advanced I/O Systems: Sp 02
• CSE 598R: Revolutionary Models of Computing: Sp 01
• CSE 598F: Processor-In-Memory Systems Sp 97

Current Graduate Students (Alphabetical)

• Timothy Dysart. M.S. Fault Tolerant QCA structures
• Alexei Koudriavtsev, Ph.D. Low Power DSP Architectures
• Sarah Frost, M.S.: QCA Memories
• Richard Murphy, Ph.D.: Traveling Threads: a New Multi-threading Execution Model
• Michael Niemier, Ph.D: QCA-Based Architectures
• Arun Rodrigues, M.S. Variable Cluster Microarchitecture

Students completing directed graduate research (By Degree Date)

• Rodrigues, Arun, M.S. CSE Dept., Univ. of Notre Dame, April 28, 2003: "RuDRA: A Reactive Dissipation Reducing Architecture."
• O'Neil, Timothy, Ph.D. CSE Dept., Univ. of Notre Dame, February 25 2002: "Techniques for Optimizing Loop Scheduling." Co-directed with Prof. Edwin Sha, now at Univ. of Texas at Dallas. Now at Univ. of Akron
• Lilia Yerosheva, M.S. CSE Dept., Univ. of Notre Dame, April 2001: "High-Level Prototyping of the HTMT Execution Models for the HTMT Petaflop Machine in Java." Now a Staff Analyst at ND
• Richard C. Murphy, M.S. CSE Dept., Univ. of Notre Dame, April 2000: "Design Parameters for Distributed PIM Memory Systems." ; Ph.D. proposal "Traveling Threads: A New model of Execution," Dec. 10, 2002
• Jason Zawodny, M.S. CSE Dept., Univ. of Notre Dame, Nov. 2000: "Cache-In-Memory: Searching for Lower Power Embedded DRAM." Now at Goodrich Aerospace
• Michael Niemier, M.S. CSE Dept., Univ. of Notre Dame, March 2000: "Designing Digital Systems in Quantum Cellular Automata". Now a Ph.D. student at ND
• Victor Zyuban, Ph.D. CSE Dept., Univ. of Notre Dame, March 2000: "Inherently Lower Power High Performance Superscalar Architectures." Now at IBM Research, Yorktown, NY.
• Steven Dartt, M.S. CSE Dept., Univ. of Notre Dame, Nov. 1998, "Exasphere: A Prototype for a Parallel "Processor-In-Memory" Architecture"
• Lakshmi Nanayanaswamy: M.S. CSE Dept., Univ. of Notre Dame, Oct. 1997, "Combinators In Memory: An Alternate Parallel Execution Model"
• John David Bezek: Ph.D., SUNY Binghamton, 1993, "Decision Table Language and Its Parallel Execution Architecture with Applications in Expert Systems"

Member of Dissertation Committee for following:

• Hongchao (Stephanie) Liu , M.S. CSE Dept., Univ. of Notre Dame, Dec. 10, 2002: "Processor Utilization Bounds for Real-Time Systems with Precedence Constraints."
• Thomas Smith, M.S. CSE Dept., Univ. of Notre Dame, Dec. 3, 2002: "Meaningful I/O System Call Analysis."
• Robert Minnerick, M.S. CSE Dept., Univ. of Notre Dame, Nov. 26, 2002: "Feedback Adaptive Energy Control."
• Jucain Butler, M.S. CSE Dept., Univ. of Notre Dame, July 8, 2002: "A Web-based, Self-Paced Tutorial on Computer Architecture for an Introduction to Engineering Course."
• Paul Schermerhorn, M.S. CSE Dept., Univ. of Notre Dame, April 11, 2002, "A Platform for Prototyping PIMOS System Services."
• Vsevolod Panteleenko, Ph.D. CSE Dept., Univ. of Notre Dame, Feb. 14, 2002: "Instantaneous Offloading of Web Server Load."
• Kevin Xin He, Ph.D. EE Dept., Univ. of Notre Dame, April 2001: "Supervisory Control of Distributed Systems Using Petri Nets and Network Unfolding."
• Yuhui Zhu, M.S. CSE Dept., Univ. of Notre Dame, Nov. 2000: "The Wave Digital PDE Sumulation Methods: Local Passivity Considerations for Nonliner PDE Systems."
• Ovidiu Daescu, Ph.D. CSE Dept., Univ. of Notre Dame, April 2000: "On Geometric Optimization Problems"
• Chantana Chantrapornchai, Ph.D. CSE Dept., Univ. of Notre Dame, April 1999: "System Level Synthesis Considering Impreciseness based on Fuzzy Theory"
• Sissades Tongsima, Ph.D. CSE Dept., Univ. of Notre Dame, April 1999: " Loop Scheduling for Applications with Fixed or Probabilistic Timing"
• Dominic Bartek, M.S. CSE Dept., Univ. of Notre Dame, 1998: "Design and Evaluation of an At-the-Sense-Amplifier Datapath."
• Kartik Nanda, M.S. CSE Dept., Univ. of Notre Dame, 1998: Analysis and Optimization of Processor-in-Memory Organizations."
• Richard Kendall. M.S. CSE Dept., Univ. of Notre Dame: "The Modify-on-Access File System."
• Kevin Klenck, Ph.D. CSE Dept., Univ. of Notre Dame
• David R. Surma, Ph.D. CSE Dept., Univ. of Notre Dame, April 1998, "Collision Graph Based Communication Scheduling and Applications."
• Arun Lokanathan, Ph.D. CSE Dept., Univ. of Notre Dame, April 1998, "Concurrent Process Multi-Circuit Optimization."
• Robert J. Szczerba, CSE Dept., Univ. of Notre Dame
• Michael J. Sheliga, Ph.D. CSE Dept., Univ. of Notre Dame, April 1997: "Efficient High Level Synthesis using Hardware/Multi-Software Co-Design and Communication Minimization"
• Nelson Passos, Ph.D. CSE Dept., Univ. of Notre Dame, June 1996: "Improving Parallelism in Multi-Dimensional Applications: The Multi-Dimensional Retiming Framework"
• Neelima Mehdiratta, Ph.D. CS Dept. State Univ. of New York at Binghamton, Aug. 1994: "A General Strategy for Scheduling Parallel Programs on Distributed Memoryt Multiprocessors."
• Andres Jaramillo, M.S. CS Dept. State Univ. of New York at Binghamton, Dec. 1989: "RIPE: A RISCy Processing Element for Loosely-Coupled Multiprocessors."