Patents and Disclosures by Peter M. Kogge:

1. Kogge, Peter M., et al, “G4-FETs: Dynamically reconfigurable memory/logic circuits and enhanced devices,” Provisional Patent filed 10/22/08.
2. Kogge, Peter M., "Low Cost-Time-out Detection in Shared Interfaces with Potentially Large Numbers of Concurrent Outstanding Requests," U.S. Patent 7,639,628, issued 12/29/2009.
3. Kogge, Peter M., et al. “Computer Architectures with Lightweight Multithreaded Architectures,” U.S. Patent 7,584,332, issued 9/1/2009.
4. Kogge, Peter M., "Architectures for Self-Contained, Mobile, Memory Programming," U.S. Patent 7,185,150, issued 2/27/2007.
5. Dieffenderfer, James Warren, Kogge, Peter M., Wilkinson, Paul Amba, and Nicholas Jerome Schoonover, "SIMD/MIMD processing synchronization," US Patent 6,094,715, issued 7/25/2000
6. Dieffenderfer, James Warren, Kogge, Peter M., Wilkinson, Paul Amba, and Nicholas Jerome Schoonover, "SIMD/MIMD array processor with vector processing," US Patent 5,966,528, issued 10/12/1999
7. Dieffenderfer, James Warren, Kogge, Peter M., Wilkinson, Paul Amba, and Nicholas Jerome Schoonover, "Partitioning of processing elements in a SIMD/MIMD array processor," US Patent 5,878,241, issued 3/2/1999
8. Dieffenderfer, James Warren, Kogge, Peter M., Wilkinson, Paul Amba, and Nicholas Jerome Schoonover, "Array processor with asynchronous availability of a next SIMD instruction," US Patent 5,870,619, issued 2/9/1999
9. Barker, Thomas Norman; Collins, Clive Allan; Dapp, Michael Charles; Dieffenderfer, James Warren; Grice, Donald George; Kogge, Peter Michael; Kuchinski, David Christoper; Knowles, Billy Jack; Lesmeister, Donald Michael; Miles, Richard Ernest; Nier, Richard Edward; Retter, Eric Eugene; Richardson, Robert Reist; Rolfe, David Bruce; Schoonover, Nicholas Jerome; Smoral, Vincent John; Stupp, James Robert; Wilkinson, Paul Amba, "Advanced parallel array processor (APAP)," US Patent 5,842,031, issued 11/24/1998.
10. Wilkinson, Paul Amba, Dieffenderfer, James Warren, Kogge, Peter M., "Array processor having grouping of SIMD pickets," US Patent 5,828,894, issued 10/27/98
11. Dieffenderfer, James Warren, Kogge, Peter M., Wilkinson, Paul Amba, and Nicholas Jerome Schoonover, "Associative parallel processing system," US Patent 5,765,015, issued 10/13/98
12. Wilkinson, Paul Amba, Baker, Thomas Norman, Dieffenderfer, James Warren, Kogge, Peter M., "Picket autonomy on a SIMD machine ," US Patent 5,815,723, issued 9/23/98
13. Wilkinson, Paul Amba, Dieffenderfer, James Warren, Kogge, Peter M., and Nicholas Jerome Schoonover, "SIMIMD array processing system ," US Patent 5,805,915, issued 9/8/98
14. Wilkinson, Paul Amba, Dieffenderfer, James Warren, Kogge, Peter M., "Floating point for simd array machine," US Patent 5,809,292, issued 9/15/98
15. Wilkinson, Paul Amba, Dieffenderfer, James Warren, Kogge, Peter M., and Nicholas Jerome Schoonover, "Slide network for an array processor," US Patent 5,765,015, issued 6/09/98
16. Wilkinson, Paul Amba, Dieffenderfer, James Warren, Kogge, Peter M., and Nicholas Jerome Schoonover, "Controller for a SIMD/MIMD Array Having an Instruction Sequencer Utilizing a Canned Routine Library," US Patent 5,765,012, issued 6/09/98
17. Wilkinson, Paul Amba, Dieffenderfer, James Warren, Kogge, Peter M., and Nicholas Jerome Schoonover, "Parallel processing system having a synchronous SIMD processing with processing elements emulating SIMD operation using individual instruction streams," US Patent 5,765,011, issued 6/09/98
18. Wilkinson, Paul Amba, Dieffenderfer, James Warren, Kogge, Peter M., and Nicholas Jerome Schoonover, "Parallel processing system having asynchronous SIMD processing and data parallel coding," US Patent 5,761,523, issued 6/2/98
19. Wilkinson, Paul Amba, Dieffenderfer, James Warren, Kogge, Peter M., and Nicholas Jerome Schoonover, "Parallel processing system having asynchronous SIMD processing," US Patent 5,754,871, issued 5/19/98
20. Wilkinson, Paul Amba, Dieffenderfer, James Warren, Kogge, Peter M., and Nicholas Jerome Schoonover, "Fully scalable parallel processing system having asynchronous SIMD processing," US Patent 5,752,067, issued 5/12/98
21. Wilkinson, Paul Amba, Dieffenderfer, James Warren, Kogge, Peter M., and Nicholas Jerome Schoonover, "Autonomous SIMD/MIMD processor memory elements," US Patent 5,717,944, issued 2/10/98
22. Barker, Thomas Norman, Kogge, Peter M., et al , "Advanced parallel array processor (APAP)," US Patent 5,717,943, issued 2/10/98
23. Wilkinson, Paul Amba, Dieffenderfer, James Warren, Kogge, Peter M., and Nicholas Jerome Schoonover, "Slide bus communications functions for SIMD/MIMD array processor," US Patent 5,713,037, issued 1/27/98
24. Barker, Thomas Norman, Kogge, Peter M., et al., "Advanced parallel array processor (APAP)," US Patent 5,710,935, issued 1/20/98
25. Wilkinson, Paul Amba, Dieffenderfer, James Warren, Kogge, Peter M., and Nicholas Jerome Schoonover, " SIMD/MIMD inter-processor communication," US Patent 5,708,836, issued 1/13/98
26. Olnowich, Howard Thomas, Barker, Thomas Norman, Kogge, Peter M., and Gilbert Clyde Vandling III, "Priority broadcast and multi-cast for unbuffered multi-stage networks," US Patent 5,680,402, issued 10/21/97
27. Wilkinson, Paul Amba and Kogge, Peter M., "Array processor dotted communication network based on H-Dots," US Patent 5,630,162, issued 4/27/95
28. Bezek, John D. and Kogge, Peter M., " Method for interfacing applications with a content addressable memory," US Patent 5,615,360, issued 3/25/97
29. Bezek, John D. and Kogge, Peter M., " Inferencing production control computer system," US Patent 5,615,309, issued 3/25/97
30. Smoral, Vincent J. Kogge, Peter M., and Sementille, Phillip J., " Hybrid Architecture for Video On Demand Servers," US Patent 5,608,448, issued 3/4/97
31. Barker, Thomas Norman, Kogge, Peter M., et al , "Advanced parallel array processor (APAP)," US Patent 5,590,345, issued 12/31/96
32. Bezek, John D. and Kogge, Peter M., "Refraction algorithm for production systems with content addressable memory," US Patent 5,579,441, issued 11/26/96
33. Bezek, John D. and Kogge, Peter M., "Inferenceing production control computer system," US Patent 5,517,642, issued 5/14/96
34. Kogge, Peter M., "Dynamic multi-mode parallel processing array," US Patent 5,475,856, issued 12/12/95
35. Brodnax, Timothy B., Bullis, Bryan K., King, Steven A., Kogge, Peter M., and Dale A. Rickard, "Data processing system having prediction by using an embedded guess bit of remapped and compressed opcodes," US Patent 5,463,746, issued 10/31/95
36. Olnowich, Howard T., Barker, Thomas N., Kogge, Peter M., and Gilbert Clyde Vandling III, "Dual priority switching apparatus for simplex networks," US Patent 5,444,705, issued 8/22/95
37. Kogge, Peter M., G. Vandling, L.A. Watson, E.W. Buterbaugh, H.T. Olnowich, "Hiding of Store Protection Checks in a Pipelined Computer," Published in IBM Tech. Disc. Bulletin, 5/92
38. Kogge, Peter M., T.W. Giambra, W. Land, Jr, "Hybrid Artificial Neural System (ANS)/Expert System," Published in IBM Tech. Disc. Bulletin, 6/90
39. Kogge, Peter M., K.T. Truong, D.A. Rickard, R.L. Schoenike, "Checkpoint Retry Mechanism," US Patent 4,912,707, issued 3/27/90
40. Kogge, Peter M., "Skewed Matrix Address Generator," US Patent #4,370,732, issued 1/25/83
41. Kogge, Peter M., "Data Communication Bus Structure," US Patent # 4,085,448, issued 4/18/78
42. Kogge, Peter M., "Program Pipeline Recurrence Problem," Published IBM Tech. Disc. Bulletin, 12/73