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How do I use the MicroStamp11's SPI subsystem?

The MicroStamp11's SPI interface uses four pins. These are pins 15-18. They correspond to bits PD2 through PD5 on PORTD. The clock line comes out of pin PD4 with the logical name SCK. This line is a 50 percent duty cycle clock whose rate can be controlled by the programmer. There are two data lines. The master-out slave-in (MOSI) line is on pin PD3. It is used to clock data out to the slave device from the MicroStamp11. The master-in slave-out (MISO) line is on pin PD2. This pin is used to clock data into the MicroStamp11 from the slave device. In addition to the clock and data lines, there is an additional control line with the logical name SS (slave select) This control line is on pin PD5. The slave-select (SS) pin is an optional control line that can be used when the channel is active. It is often used to signal the end or beginning of a transmission.

Figure 5 shows how the SPI interface is constructed. The data (MOSI/MISO) pins are connected to an 8-bit data register with logical name SPDR. When a data transfer operation is performed, this 8 bit register is serially shifted eight positions and the data is transmitted to or received from the slave. Figure 5 illustrates the pins and their connection to the SPDR buffer assuming that a serial IC (ADC0831) is clocking data into the MicroStamp11 over the MISO pin.

Figure 5: MicroStamp11's SPI subsystem
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Using the SPI subsystem to output data to the shift register is relatively easy with the kernel function provided in the lab. The kernel function is shiftout(). This function clocks out an 8 bit frame at a specified rate over the MOSI line. This function is blocking, which means that the function will not return until the data has actually been transmitted by the MicroStamp11. We've also included a function shiftin that can be used to clock data into the MicroStamp11 from the slave device. A more detailed description of both kernel functions is provided below:

For both functions the legal values for the rate argument are defined in the following table.
logical name transfer frequency
SPI_1MHz 1 MHz
SPI_500kHz 500 kHz
SPI_125kHz 125 kHz
SPI_62kHz 62.5 kHz


next up previous
Next: What is a serial-to-parallel Up: Background Previous: What is a serial
Michael Lemmon 2009-02-01