`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: University of Notre Dame
// 
// Create Date:    00:18:55 03/28/2007 
// Module Name:    processor 
// Project Name: CSE30321
// Target Devices: xc3s100e-5vq100
// Description: Implementation of the Six-instruction processor from
// Frank Vahid's Digital Design, Ch. 8 
//
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module processor(clk, start, reset,
                 i_addr, i_data,
                 d_addr, d_data, d_wdata, d_wr);
	input clk, start, reset;
	wire[3:0] RF_W_addr, RF_Rp_addr, RF_Rq_addr;
	wire[7:0] RF_W_data, D_addr;
	wire[15:0] D_R_data, D_W_data, I_R_data, pc_addr;

  output[7:0] i_addr, d_addr;
  input[15:0] i_data, d_data;
  output[15:0] d_wdata;
  output d_wr;

	datapath D(.clk(clk), 
				  .RF_W_addr(RF_W_addr),
				  .RF_W_wr(RF_W_wr), 
				  .RF_Rp_addr(RF_Rp_addr), 
				  .RF_Rp_rd(RF_Rp_rd), 
				  .RF_Rq_addr(RF_Rq_addr), 
				  .RF_Rq_rd(RF_Rq_rd), 
				  .RF_s1(RF_s1), 
				  .RF_s0(RF_s0), 
				  .alu_s1(alu_s1), 
				  .alu_s0(alu_s0),
				  .RF_W_data(RF_W_data),
				  .R_data(D_R_data),
				  .RF_Rp_zero(RF_Rp_zero),
				  .RF_Rp_lt(RF_Rp_lt),
				  .rp(D_W_data),
				  .reset(reset)
				 );
				 
	control C(.clk(clk),
				 .start(start),
				 .reset(reset),
				 .RF_W_addr(RF_W_addr),
				 .RF_W_wr(RF_W_wr),
				 .RF_Rp_addr(RF_Rp_addr),
				 .RF_Rp_rd(RF_Rp_rd),
				 .RF_Rq_addr(RF_Rq_addr),
				 .RF_Rq_rd(RF_Rq_rd), 
				 .RF_s1(RF_s1),
				 .RF_s0(RF_s0),
				 .alu_s1(alu_s1),
				 .alu_s0(alu_s0),
				 .RF_W_data(RF_W_data),
				 .inst(I_R_data),
				 .I_rd(I_rd),
				 .RF_Rp_zero(RF_Rp_zero),
				 .RF_Rp_lt(RF_Rp_lt),
				 .D_rd(D_rd),
				 .D_wr(D_wr),
				 .D_addr(D_addr),
				 .pc_addr(pc_addr)
					);
/*	
	data_mem DM (
		.clka(clk),
		.dina(D_W_data), 
		.addra(D_addr), 
		.wea(D_wr),
		.douta(D_R_data)
	);
	
	inst_mem IM (
		.clka(clk),
		.addra(pc_addr),
		.douta(I_R_data)
	); 
*/

  assign i_addr = pc_addr;
  assign I_R_data = i_data;

  assign d_addr = D_addr;
  assign D_R_data = d_data;
  assign d_wdata = D_W_data;
  assign d_wr = D_wr;
endmodule