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Computer Architecture I

CSE 30321
101 Jordan Hall of Science
Tuesday/Thursday, 11:00 a.m. - 12:15 p.m.
On Twitter (CSE_30321)

Course
Objectives

By the end of this course you should be able to:

  1. Employ established architectural performance metrics to explain why one microprocessor might be able to outperform another.
  2. Describe the fundamental components required in a single core of a modern microprocessor and how they interact with each other, with main memory, and with external storage media.
  3. Explain how code written in a high-level language (like C) is eventually executed “on-chip” to produce the result intended by the programmer.
  4. Explain and articulate why modern microprocessors now have more than one core.
  5. Suggest, compare, and contrast potential architectural enhancements by applying appropriate performance metrics.
  6. Apply fundamental knowledge about single core machines, dual core machines, performance metrics, etc. to design a microprocessor such that it (a) meets a target set of performance goals and (b) is realistically implementable.

Final
Grades

Your final course letter grade can be found (here).

Course
Schedule
Date Day Topic Suggested Reading HWs Labs
1 Aug. 25 T
  • Course Introduction, Technology Review, Logic Design, Syllabus, and Logistics
  • Lecture Notes (PDF)
  • Syllabus (PDF)
Vahid, Chapter 8
2 Aug. 27 H
  • Programmable Processors + 3 Instruction Processor
  • Lecture Notes (PDF)
HW 1 out
3 Sep. 1 T
  • 3 Instruction Processor + 6 Instruction Processor
  • Lecture Notes (PDF)
Lab 1 out
Lab 1 Files
4 Sep. 3 H
5 Sep. 8 T
  • Architectural Performance Metrics
  • Lecture Notes (PDF)
P&H Chapter 1 HW 1
due
HW 2 out
Datapath
FSM
 Lab 2 out
Lab 2 Files
6 Sep. 10 H
  • Performance Metrics + MIPS ISAs
  • Lecture Notes (PDF)
P&H Chapter 2.1-2.3
2.5-2.7		 Lab 1
due
7 Sep. 15 T
  • MIPS Assembly
  • Lecture Notes (PDF)
P&H Chapter 2.1-2.3
2.5-2.7		 HW 2
due
HW 3 out 		Lab 3 out
Lab 3 Files
8 Sep. 17 H
  • MIPS Assembly Examples + MIPS Procedure Calls
  • Lecture Notes (PDF)
P&H Chapter 2.8
2.13 useful		 Lab 2
due
9 Sep. 22 T
  • MIPS Procedure Calls
  • Lecture Notes (PDF)
  • Examples (1) (PDF)
  • Examples (2) (PDF)
P&H Chapter 2.8
2.13 useful		 HW 3
due
HW 4 out 		Lab 4 out
Lab 4 Files
10 Sep. 24 H
  • MIPS Procedure Calls (Examples)
  • Lecture Notes (PDF)
  • Example Handout (PDF)
P&H Chapter 2.8
2.13 useful		 Lab 3
due
11 Sep. 29 T
  • Single Cycle Processor Design
  • Lecture Notes (PDF)
P&H Chapter 4.1-4.4 HW 4
due
HW 5 out 		Lab 5 out
Lab 5 Files
12 Oct. 1 H
  • Single Cycle Processor Design
  • Lecture Notes (PDF)
  • Examples (PDF)
P&H Chapter 4.1-4.4 Lab 4
due
13 Oct. 6 T
  • Single Cycle Processor Design (Control Logic & Limitations)
  • Lecture Notes (PDF)
  • Examples (PDF)
P&H Chapter 4.1-4.4
14 Oct. 8 H
  • Single Cycle Processor Design
    (Limitations + Solutions)
    (lw / sw review)
  • No new notes.
HW 5
due 		Lab 5 Parts C, D
due
15 Oct. 13 T
  • Midterm Review
  • Lecture Notes (PDF)
16 Oct. 15 H In Class Midterm
Oct. 16 F
Oct. 20 T No Class: Fall Break
Oct. 22 H No Class: Fall Break
17 Oct. 27 T
  • The Multi-Cycle Processor
  • Lecture Notes (PDF)
P&H Chapter 4.1-4.4
18 Oct. 29 H
  • Control for the Multi-Cycle Processor
  • Lecture Notes (PDF)
  • Examples (PDF)
P&H Chapter 4.1-4.4 HW 6 out
19 Nov. 3 T
  • Parallel Programming, Multi-core Processors, Intro. to Pipelining
  • Pipelining Lecture Notes (PDF)
  • Multi-core Lecture Notes (1) (PDF)
  • Multi-core Lecture Notes (2) (PDF)
  • Pipelining Math Notes (PDF)
P&H Chapter 4.5-4.6 Lab 5 Part E
due (in class)
Lab 6 out
Paper
Evaluation
20 Nov. 5 H
  • Pipelining
  • Lecture Notes (PDF)
  • Hazard Notes (PDF)
P&H Chapter 4.7 HW 6
due
HW 7 out
21 Nov. 10 T P&H Chapter 4.8
22 Nov. 12 H
  • Pipelined Processors + Introduction to Caches
  • Cache Lecture Notes (PDF)
  • Pipetrace Examples Part 2 (PDF)
  • Pipetrace Examples Part 3 (PDF)
P&H Chapter 5.1 HW 7
due
23 Nov. 17 T P&H Chapter 5.1 HW 8 out Lab 6 due
(in class)
Final Project
out
24 Nov. 19 H
  • Cache Examples
  • Lecture Notes (PDF)
  • Cache Examples (PDF)
25 Nov. 24 T
  • Cache Optimizations +
    Architectural Support for Virtual Memory
  • Lecture Notes (PDF)
  • Board Notes (PDF)
Nov. 26 H No Class: Thanksgiving
26 Dec. 1 T
  • Architectural Support for Virtual Memory
  • Example 1 (PDF)
  • Example 2 (PDF)
HW 8
due
HW 9 out
27 Dec. 3 H
  • Memory Hierarchies, Storage, and I/O
  • Lecture Notes (PDF)
  • Board Notes (PDF)
Baseline Benchmarks
due
28 Dec. 8 T
  • Parallel Processing and Multi-core Architectures
  • Lab 06 Feedback (PDF)
  • Lecture Notes (PDF)
29 Dec. 10 H
  • Final Exam Review / Course Recap
  • Practice Final (PDF)
  • Practice Final Solutions (PDF)
  • Review Slides (PDF)
HW 09
due 		Final Project
due
Dec. 11 F Final Project
due
Dec. 18th F In Class Final Exam - 10:30 - 12:30 - 101 Jordan

Lab
Resources

Lab resources and handouts can be found here.

Required
Texts
  • David A. Patterson and John L. Hennessy, Computer Organization and Design: The Hardware/Software Interface, 4th Ed., Morgan Kaufmann Publishers, ISBN 978-0-12-374493-7.
  • Frank Vahid, Digital Design, John Wiley & Sons, Inc., 2007.

Contact
Information

Instructor

  • Michael T. Niemier(mniemier@nd.edu)
    380 Fitzpatrick Hall
    Notre Dame, IN 46556
    (574) 631-3858

    Office Hours: Wednesday -- 9:30-11:00; Thursday -- 1:00-2:30

Graduate TAs

  • Aaron Dingler (afs id = adingler)

    Office Hours: Monday, 2-3 pm (300 Cushing)

  • Zhi Zhai (afs id = zzhai)

    Office Hours: Tuesday, 5-6 pm

Undergraduate TAs

  • Daniel Moeller (afs id = dmoeller)

    Office Hours: Monday, 3-4 pm (208 Cushing)

  • Jared Zenk (afs id = jzenk)

    Office Hours: Thursday, 2-3 pm (208 Cushing)