My
research interests span several areas including circuit and architecture design with emerging
technologies, energy and reliability
aware system design, resource
management for real-time embedded systems, hardware-software co-design, and
computational medicine. The underlying characteristic common to these areas is
the employment of algorithm and/or hardware design and analysis techniques to
solve problems arising from real-world applications.
As
the CMOS transistor feature size is approaching its physical limit, we are
witnessing an explosion of research endeavors in beyond-CMOS technologies. My
work explores circuit and architecture designs that can best exploit the unique
features of beyond-CMOS devices to maximize the gain offered by such devices.
My research benefits greatly from close collaborations with device experts.
Below are the several representation topics.
Processing
in memory (PIM) is an attractive architectural
paradigm for overcoming the ever-growing challenge of transferring data between a
processing element and memory
in applications such as machine learning and data analytics applications.
Beyond-CMOS devices, such as ferroelectric FETs (FeFETs),
can function both as a switch and a storage element, hence is a natural fit for
implementing PIM constructs. My group have introduced various FeFET based content addressable memories (e.g., ternary,
approximate, multi-bit), general-purpose compute-in-memory
arrays, binary crossbars
arrays, etc.
A paper
introducing an FeFET based compute-in-memory array,
co-authored by my Ph.D. student, Dayane Reis, my
colleague Mike Niemier and I, received the Best Paper
Award from 2018 International Symposium on Low Power Electronics and
Design. Another paper
from my group received the Best Paper Award from 2009 International
Symposium on NanoScale Architectures. Below are other
representative papers.
·
A.F.
Laguna, H. Gamaarachchi, X. Yin, M. Niemier, S. Parameswaran and X. Hu, “Seed-and-vote
based in-memory accelerator for DNA read mapping”, International Conference on Computer Aided Design, 2020. Article
No. 56, pp. 1–9.
·
B. Wu, C. Wang,
Z. Wang, Y. Wang, D. Zhang, D. Liu, Y. Zhang and X. Hu, “Field-free
3T2SOT MRAM for non-volatile cache memories”, IEEE Transactions on Circuits and Systems, 2020, pp. 4660–4669.
·
D.
Reis, A.F. Laguna, M. Niemier and X. Hu, “A fast and energy efficient
Computing-in-Memory architecture for few-shot learning applications”, Design Automation and Test in Europe, 2020,
pp. 127–132.
Secure
hardware and hardware for security. Some unique characteristics, such as
ambipolarity, of beyond-CMOS devices make these
devices especially suited for building low-cost, secure hardware circuits. My
group have introduced several novel circuits to achieve logic obfuscation
and/or prevent side channel attacks. We also proposed accelerators for
homomorphic encryption. Below are some representative papers.
For
more detailed description about my research projects in this area, please visit
my group at: Nanomagnet Logic Research Group
My
earlier research in the general circuit and architecture design is related to
VLSI design and design automation. I have studied problems in high-level
synthesis, VLSI floorplanning, and design of special
VLSI circuitry for computationally intensive systems.
For
electronic systems, energy/power consumption and reliability are critical
concerns due to their impact on the system cost and the environment. My work
exploits characteristics of both applications (such as real-time control and
multimedia) and underlying hardware (such as GPUs and heterogeneous multi-core SoCs) to design online and offline techniques to reduce
energy and improvement reliability. Below are some representative papers:
My
former Ph.D. student, Gang
Quan, and I received the Best Paper
Award from 2001 Design Automation Conference for our work
on power-aware scheduling for fixed-priority real-time systems. Another
paper co-authored by us was recognized as one of the Most
Influential Papers of 10 Years at 2007 Design, Automation, and Test in
Europe Conference (DATE).
In a
related research area, I have worked on acceleration techniques for
computational problems that arise in medical applications. For instance, I have
studied problems in radiation therapy, a minimally invasive surgical procedure
that uses a set of focused beams of radiation to destroy tumors. My students,
colleagues and I have introduced novel algorithms as well as GPU and FPGA based
acceleration approaches for radiation treatment planning, radiation dose
calculation and deformable image registration.
Besides requiring
correct results, real-time applications (such as vehicle control and
navigation) also demand the results be produced at the right time. Resource
(e.g., computing and network fabrics) management allocates services to
different tasks in the system to meet such timing requirements. I have worked
on management techniques for both computing and networking resources under
different types of timing specifications. My recent focus is on distributed approaches
in wireless sensor and actuator networks. Below are some representative papers:
My
research projects have been supported by a number of sources including
· National Science Foundation (NSF):
o
CCF:
Software and Hardware Foundations (Faculty Early Career Development
(CAREER) Award)
o
CNS:
Computer Systems Research
·
Defense Advanced Research
Projects Agency (DARPA)
·
Semiconductor Research Corporation (SRC)