Student Educational Objectives

1. articulate the big picture encompassing various facets of the digital integrated circuit design and manufacturing process, including explaining:
   • the relationships between levels of abstraction in modern silicon-based logic system design, such as device level, gate level, logic level, system level
   • the correspondence between the mask layers used in CMOS physical design and manufacturing process steps, as well as explain what design rules are and how they are defined
   • some of the basic design styles and cost/performance tradeoffs between them including, full-custom, standard cells, and gate array
2. demonstrate a basic working knowledge, through homework and short projects of a set of topics including:
   • Basic MOSFET based logic families, and the functioning of basic circuits,
   • MOS transistor IV characteristics
   • DC behavior of CMOS static logic circuits, voltage transfer characteristic, and how their characteristics change with different transistor implementation parameters.
   • transient behavior of CMOS static logic circuits, including propagation delay and dynamic power dissipation
   • cell layout and area estimation techniques, based on sticks diagrams and Euler paths
   • use of a suite of CAD tools for design and simulation
   • design of sequential circuits, flip-flops and registers
   • approximate transistor parameters (resistance and capacitance) from dimensions
   • tradeoff transistor sizes for delay and power
   • compute logical effort & overall delay in a multistage CMOS circuit, and size transistors to minimize such delay
   • tradeoffs in design of basic system building blocks, including memory, adders, multipliers, and shifters
   • tradeoffs in interconnect of multiple such building blocks, and their clocking
   • computing static and dynamic power at the system level, and power-saving mechanisms
3. show a working knowledge of future trends in silicon and how quickly estimate how area, speed, and power of CMOS digital systems will change as technology shrinks

Difference from prior offerings:

• The class no longer satisfies the capstone design requirements for CPEGs as there is no semester design project.
• There will be more coverage of system level topics of critical importance to modern digital chips, such as CMOS scaling, power, I/O, memory, and alternative design approaches such as FPGAs.
• Verilog-level design work will be made optional.
• There will be discussions at the end of the semester on emerging alternative device technologies of relevance to digital designs.
• Analog topics such as current mirrors, operational amplifiers, transistor matching, and D/A and A/D converters are no longer covered.