VLSI Design
CSE/EE 40462/60462
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Class Notes
For Exam 1
Course Mechanics
Introduction
CMOS Circuits Part A
CMOS Circuits Part B
CMOS Circuits Part C
Basic CMOS Fab Process
Intro to Design Rules
Standard Cells and Stick Figures
In class review of
Electric Layout tool
using
Tutorial for Electric
Euler Paths in Stick Figures
: 1 -
Programmable Logic
For Exam 2
180nm Transistor Curve
MOSFETs-B: IV Curves
MOS-IV-V2 Spreadsheet
MOSFET-C Real-World Effects
Basic CMOS Fabrication Processing
MOSFETs-A: Ideal Equations
Design Rules
Layout and Stick Figures
Euler Paths in Stick Figures
Scaling
Memory A
Memory B
Programmable Logic
Verilog
For Exam 3
Delay-A
Delay-B
Logical Effort A
Logical Effort B
Flash Memory
Power
FeFETs
Prof. Miemier Guest Lecture
Extra Material on Verilog
Intro to Verilog Using Book's 8-bit MIPS
8-bit MIPS Summary
8-bit MIPS - Structural Verilog
8-bit MIPS - Behavioral Verilog
Other
Semester Design Project
Copyright © Peter Kogge 2012