VLSI Design
CSE/EE 40462/60462
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Web Site Complete Change Log
11/13:
Exam 2
is now posted. Due into my box in 384Fitz by Friday at 5pm.
11/9: Note switch in speaker days for next week.
11/9: Schedule updated and answers to homeworks posted. HW5 and 6
solutions
found here. Remember:
Individual microprocessor project
Presentations Tu. Nov. 27
10/29: Slides for Last Tuesday's Lecture on
Processing Near Memory
. Slides for
Memory
Posted.
Homework 6
due Th 11/8.
10/12: The
CMOS IV Spreadsheet
has been posted. See the first sheet for instructions on use.
10/9: Individual historical microprocessor project posted; Added link to
TPUs as Systolic Arrays
10/5: Change to Guest lecturer for 10/23: Prof: Siddharth Joshi will talk abut architectures for ML and "ML in Memory"
10/4: Added some references to TPU to "Real Chips" page
10/1:
Exam 1. Due Wed 10/3 5pm.
10/1:
Thoughts on Project
9/26: HW 4 revised a bit; review topics for exam posted
9/25: lots of Intel 4004 extra pointers added
9/20: Change of deadline for HW3 to Wed. 5pm
9/14: Exam 1 scheduled for Tu Oct. 2 on material thru Scaling (and Homework 3).
9/12:
Tutorial for Electric
posted. Also added to Links
A simple online circuit simulator
9/10: Homework 2 changed.
8/23: first posting
Copyright © Peter Kogge 2012