Project

• The final project hadnout can be found here.
• This lab can be done in three or four person groups. See the handout for intermediate deadilnes.
• Benchmarks can be found here: Bubblesort, Fibonacci, Branches.
• Note: the original "branches" benchmark used a JUMPNZ instruction -- which is not something that you initially implemented. A revised version of the benchmark can be found here.
• The Verilog files for a baseline design can be found here.
• A document that explains how to estimate ADP can be found here. The processor.v file that the area document references can be found here.

Lab 6

• Lab Assignment 6 can be found here.
• This lab can be done in two-person groups. Your report is due in lab the week of November 17th. Note that this lab requires more independent design; you are given two weeks but start early!
• The Verilog files can be found here.
• A supplementary PDF with additional questions to answer can be found here.

Lab 5

• Lab Assignment 5 can be found here.
• This lab can be done in two-person groups. Your report is due in lab the week of November 5th.
• The Verilog files can be found here.
• The ArrayAccess.s file can be found here.
• The README for the new simulator can be found here.
• The code for the new simulator can be found in /afs/nd.edu/courses/cse/cse30321.01/labs/psim/

Lab 4

• Lab Assignment 4 can be found here.
• This lab can be done in two-person groups. Your report is due Friday October 17th.
• The XSPIM tutorial can be found here.

Lab 3

• Lab Assignment 3 can be found here.
• This lab can be done in two-person groups. Your report is due in lab the week of October 5th.
• Useful Links for Lab 3
  • Verilog files: zip
  • Tutorial: tutorial
  • No new additional questions were added or will be added to the lab. However, the section discussing what you need to turn in for your report has been modified slightly and a new PDF has been linked above.

Lab 2

• Lab Assignment 2 can be found here.
• This lab can be done in two-person groups. Your report is due in lab the week of September 21st.
• Useful Links for Lab 2
  • Verilog files: zip
  • Online Simulator: (local Java applet) or (Vahid Java applet)

Lab 1

• Lab Assignment 1 can be found here.
• This lab can be done in two-person groups. Your report is due in lab the week of September 7th.
• Come to your lab session prepared to demo with your group. The TAs will try to get everyone on a first come, first serve basis. (See the e-mail from Aaron on 9/9).
• Useful Links for Lab1
  • CSE20221 Keyboard Interface Project: pdf
  • CSE20221 Verilog Handout: pdf
  • CSE20221 Verilog FSM Handout: pdf
  • CSE20221 Verilog, Xilinx video tutorials: html (requires Flash and JavaScript)
  • ModelSim Tutorial: html (requires Flash and JavaScript)
  • Verilog files: zip
  • Basys TQ144 Reference Manual: pdf